1. Field of the Invention
This invention relates to the testing of interconnects in an electronic system, and more particularly, to the testing of high-speed links.
2. Description of the Related Art
Plesiochronous signaling is a form of high-speed signaling capable of transfer rates of up to 10 Gbits/s over a single interconnection. As such, plesiochronous links are capable of significantly higher data transfer speeds than traditional synchronous links (synchronized to a global clock) or source synchronous links (synchronized by a clock transmitted concurrently with the data). Instead of relying on a separate clock signal, plesiochronous links utilize an embedded clock signal, which is recovered from transmitted data by a clock-and-data recovery (CDR) circuit.
Due to the high data transfer rates and the embedded clock, plesiochronous links may be more susceptible to certain failures than synchronous or source synchronous links. The modes of failure include sensitivity to cross-talk, inter-symbol interference, jitter, and power supply glitching. Accordingly, testing of plesiochronous links must exercise the links in order to exercise these failure modes.
The nature of plesiochronous data transfer poses challenges in the testing process that are not present with synchronous and source synchronous links. In an assembled system utilizing plesiochronous signaling, the links may be tested by transmitting data from a transmitter over the links to a receiver. However, since there is no reference clock or forwarded clock associated with a plesiochronous link, synchronization between the transmitter and the receiver poses a problem in correctly interpreting the transmitted data in order to compare it with expected data. These challenges must be overcome in order to ensure sufficient testing of systems utilizing plesiochronous signaling.